Tomography of Semiconductor Materials and Device Structures

The development of laser-assisted atom-probe tomography (APT) analysis and new sample preparation approaches have led to significant advances in the characterization of semiconductor materials and device structures by APT. The high chemical sensitivity and three-dimensional spatial resolution of APT makes it uniquely capable of addressing challenges resulting from the continued shrinking of semiconductor device dimensions, the integration of new materials and interfaces, and the optimization of evolving fabrication processes. Particularly pressing concerns include the variability in device performance due to discrete impurity atom distributions, the phase and interface stability in contacts and gate dielectrics, and the validation of simulations of impurity diffusion. This overview of APT of semiconductors features research on metal-silicide contact formation and phase control, silicon field-effect transistors, and silicon and germanium nanowires. Work on silicide contacts to silicon is reviewed to demonstrate impurity characterization in small volumes and indicate how APT can facilitate defect mitigation and process optimization. Impurity contour analysis of a pFET semiconductor demonstrates the site-specificity that is achievable with current APTs and highlights complex device challenges that can be uniquely addressed. Finally, research on semiconducting nanowires and nanowire heterostructures demonstrates the potential for analysis of materials derived from bottom-up synthesis methods. Atom-Probe Tomography of Semiconductor Materials and Device Structures Lincoln J. Lauhon, Praneet Adusumilli, Paul Ronsheim, Philip L. Flaitz, and Dan Lawrence In contrast, the combined high sensitivity (~5 × 1017 cm−3 or 10 appm) and subnanometer-scale spatial resolution of atom-probe tomography (APT) suggest an important role for it in future device characterization.1,2 APT measurements also have the potential to greatly improve modeling of processes; the availability of precise and accurate information at the atomic scale in 3D is extremely useful for calibrating and validating models of impurity atom implantation and diffusion. As decreasing device dimensions necessitate the industry to move from planar silicon device technology to more complex geometrical designs such as multigate transistors, fin-shaped field-effect transistors, and tri-gate transistors, the challenge of ensuring a specific impurity distribution, and thereby a well-defined charge distribution, increases greatly. To enable APT to analyze these complex structures, a combination of top-down and bottom-up sample preparation approaches have been developed, as illustrated in Figure 1. The availability of dual-beam focused ion beam (FIB) microscopy-based sample preparation methods3,4 has enabled site-specific characterization of portions of the device structure under consideration (Figure 1c and 1d). The development of novel bottom-up approaches to nanowire growth29 has enabled the analysis of nanowire specimens grown in place (Figure 1b). The TEM image of the device in cross section (Figure 1c) shows the materials diversity in a silicon device as revealed by the contrast differences. If the APT microtip is composed of regions with differing evaporative properties, such as metal, oxide, and nitride dielectrics, the surface will field evaporate, preferentially leading to changes in surface topography. Small changes in the radius of curvature of a microtip can distort the positioning of atoms in the 3D reconstruction causing length-scale errors.2 To alleviate this problem, the device is stripped back to the semiconductor silicon features, removing the silicon oxide and nitride layers, in particular, and refilling the space with a conformal chemical vapor deposition (CVD) coating of silicon, Figure 1d. When formed into a microtip, this predominantly silicon sample will evaporate smoothly and enable accurate 3D reconstructions of the device structure. We note that the dual-beam FIB microscope must have sufficient imaging resolution to place the encapsulated device in the center of the sharp tip with less than 20 nm tolerance for placement error. The process involves cutting a wedge from the silicon wafer that includes the device, mounting this section on an analysis post, and then Metrology Challenges in Highly Scaled Semiconductors Materials characterization of semiconductors plays an essential role in the steady improvements in semiconductor technology performance and costs. As device dimensions shrink, impurity atom diffusion is strongly affected by interface proximity and segregation. The structural three-dimensional effects on diffusion and impurity activation cannot be charac terized by many conventional characte rization tools. Secondary ion mass spectroscopy (SIMS) and transmission electron microscopy (TEM) have been the main sources of information on impurity diffusion and materials structure, respectively. Shrinking device dimensions have, however, long surpassed the lateral resolution of SIMS, so diffusion studies are limited to planar structures. TEM-based techniques, including electron energy loss spectroscopy (EELS) and x-ray fluorescence, have a spatial resolution comparable to the probe diameter of 1 nm. While this spatial resolution is suitable for small geometry device analysis, sensitivity is limited for impurities; arsenic can be detected to 5 × 1020 cm−3 but not at the typical junction concentrations of ~5 ×1018 cm−3. 738 MRS BULLETIN • VOLUME 34 • OCTOBER 2009 • www.mrs.org/bulletin Atom-Probe Tomography of Semiconductor Materials and Device Structures MRS BULLETIN • VOLUME 34 • OCTOBER 2009 • www.mrs.org/bulletin 739 forming a sharp microtip with the device at its center by sputtering away material with a low-energy Ga+ ion beam. The region of the surface that is damaged by the ion beam is visible in the reconstruction and is therefore readily discarded from the subsequent analysis. By enabling high spatial resolution composition measurements in 3D in thin films and complex device structures, these and other techniques have opened up important op portunities for the design of future semiconductor devices, integration of new material systems, and optimization of the fabrication process flow to control defects and variability. Areas of particular interest, which will be addressed in this article, are the transition metal distribution in silicide contacts, impurity contour analysis in the source-drain extension regions under the gate, and the characterization of nanowire heterostructures. Silicide Contacts to Silicon As semiconductor device dimensions shrink with every technology generation, new silicide source-drain contacts (Figure 1a) have been developed. Previously used Tiand Co-silicides have now given way to Ni-based silicides primarily due to their low resistivity, lower temperature of formation, and lower silicon consumption.5 It is important to ensure the formation and retention of the low resistivity phase among the various possible silicide phases at the end of the device fabrication process. In the case of Ni-silicides, six different stable phases have been reported at room temperature. Often these phase changes deviate from the expected equilibrium phase formation sequences and are dependent on a host of process parameters, such as impurity type and fluence, substrate type, metal thickness, surface preparation, and annealing conditions, thus making fabrication of reliable contacts challenging. However, materials analysis is difficult at this small length scale. X-ray diffraction is limited due to the small volume available. TEM has compositional analysis capability at the device dimensions, but of the significant impurities, only arsenic is detectable below 1 at.%. The As concentration in the doped silicon under the Ni during silicide formation is near the As solubility limit; when this Si is consumed in the silicide formation, the rejected As accumulates at grain boundaries or interfaces. For microelectronic device optimization, this segregation needs to be minimized to retain the silicon conductivity in the contact region. High-precision characterization using APT gives us an opportunity to study not only the phase formation and evolution but also 3D impurity distributions, interface chemical roughness, and diffusion issues, all of which are relevant to the fabrication of low-resistivity contacts. NiSi is the low resistivity phase of interest for present day contact applications in complementary metal oxide semiconductor (CMOS) field-effect transistors. The main drawbacks of this system include (1) agglomeration of the desired NiSi phase, which causes an increase in the resistivity, and (2) formation of the higher resistivity NiSi2 phase during silicide processing. The addition of transition metal elements such as Pd, Pt, or Rh, however, has been shown to reduce the agglomeration of thin NiSi films and increase the formation temperature of NiSi2. Using localelectrode atomprobe (LEAP) tomography, Kim et al.8 explained the enhanced resistance to agglomeration exhibited by Pd-doped films. Figure 2b displays a proximity histogram (or proxigram) for a Ni (5 at.% Pd) thin film on Si(100) subjected to rapid thermal annealing to form a monosilicide phase followed by a post-anneal treatment to simulate the back-end-of-line process. A proxigram is a 3D nonlinear concentration profile created by calculating the average concentration within a defined voxel size as we propagate the topological shape of the isoconcentration surface in the film.9 The segregation of Pd at the NiSi/Si interface, as illustrated by the peak in Pd concentration, Figure 2b, is driven by a decrease in the interfacial Gibbs free energy. This leads to a concomitant decrease in the driving force for agglomeration of the monosilicide film and results in a stable silicide film resistant to morphological degradation during subsequent processing at elevated temperatures. Similarly, Ronsheim et al.10 observed the segregation of Pt at the NiSi/Si heterophase interface in TiN-capped Ni(Pt)Si film on n-type Si, thereby establishing interfacial segregation of transition metal elements as the predominant reason for enhanced resistance to agglomeration. Figure 3 exhibits segregation of both Pt and As dopants at the NiSi/Si interface by both TEM spectroscopy and APT. a